1. Field of the Invention
The present invention relates to a memory device such as a dynamic random access memory (DRAM) having row decoder with a reduced timing margin or a reduced through-current.
2. Description of the Related Art
For memory device, high speed operation is required with the high speed operation of micro processor unit (MPU).
FIG. 18 shows a circuit of a row address system of a prior art memory 10. N-shaped bending lines in the drawings denote long-distance wiring in a chip.
Row address having A8 through A15 bits from external is provided to the data input of a row address register 11 via a buffer gate 12A for a signal level interface, while a chip selection signal *CS (* denotes that its signal is active when it is low), a row address strobe signal *RAS, a column address strobe signal *CAS, a write enable signal *WE, a clock enable signal CKE and a clock signal CLK, which are from external, are provided via a buffer gate 12B to a control circuit 13 including a command decoder and generating various control signals. For example, as one of the control signals, a signal AS1 activated in response to issuance of an activate command is generated.
Meanwhile, a signal propagation delay time of long-distance wiring in a chip depends on the variance of parasitic resistance and parasitic capacity resulting from variance in production processes, variance per chip in power source voltage used, and changes in temperatures. Furthermore, since the distances from the pads on a chip for the row address of A8 through A15 to the row address register 11 differ from bit to bit, skews will occur among signals.
FIG. 19 are time charts showing operations of FIG. 18. In FIG. 19, each solid line shows a case where the signal propagation delay time is the mean, each dashed line and each dotted line show cases where the signal propagation delay time is the maximum and the minimum causing from the above-described reasons, respectively.
It is assumed that the row address signal ADRO and the control signal CMD0 at the outputs of the buffer gates 12A and 12B, respectively, change simultaneously at a time T1. The front edges of the row address ADR1 at the data input of the row address register 11 and the control signal AS1 as a strobe signal near the clock input CK of the row address register 11 delay from the time T1 as shown in FIG. 19.
In a case where the signal propagation delay time to the data input of the row address register 11 is the largest and the signal propagation delay time to the clock input CK of the row address register 11 is the smallest, in order to hold row addresses in the row address register 11 without error, it is necessary to delay the control signal AS1 by a time TD1 shown in FIG. 19 in a timing generation circuit 14 to generate a strobe signal AS2 and to provide it to the clock input CK of the row address register 11.
Output of the row address register 11 is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17. These complementary signal generation circuit 15, predecoder 16 and word decoder 17 constitute a row address decoder. The word decoder 17 is formed along one side of one memory block in a memory core block 18A, and the word decoder 17 is located near one side of a chip. Since the number of output lines of the complementary signal generation circuit 15 is twice as many as that of input lines, the circuit 15 and 16 are formed near the word decoder 17 to decrease the length of many lines. Since a memory core block 18B is formed to-be symmetrical with the memory core block 18A and a word decoder in the memory core block 18B is formed near the opposite side of the chip, the row address register 11 is formed near the middle point between the memory core blocks 18A and 18B.
Therefore, the wiring from the row address register 11 to the complementary signal generation circuit 15 is long.
Memory cells (not shown) in row are coupled to each word line WL shown with dotted line in FIG. 18 and the word lines are connected to the output of the word decoder 17. Memory cells (not shown) in column are connected to bit lines BL and *BL which are connected to a circuit 19 including a sense amplifier, a precharge circuit and a column gate. Memory cells in a row are selected with an activate word line and contents thereof are read onto bit lines. Since the word decoder 17 is provided with a logic gate circuit for each word lines WL, there is no allowance for arranging other circuits in this circuit area. If there is a skew among the edges of the input signal to the word decoder 17, an erroneous word line will be selected for a moment.
Therefore, in order to secure the output timing of the word decoder 17, the timing of the output PDA0 of the, predecoder 16 at the preceding stage is secured. Namely, a signal S1 on the same line of the control signal AS1 is delayed at a timing generation circuit 20 to generate a strobe signal S2, and this signal is provided to the predecoder 16.
The output ADR2 of the row address register 11, the input ADR3 of the complementary signal generation circuit 15, the output CADR0 of the circuit 15 and the input CADR1 of the predecoder 16 are delayed one after another as shown in FIG. 19.
As in the above description, in a case where the signal propagation delay time to the data input of the predecoder 16 is the largest and the signal propagation delay time to the strobe signal input of the predecoder 16 is the smallest, in order to prevent the output signal PDA0 of the predecoder 16 from a skew, it is necessary to delay the signal S1 by a time TD2 shown in FIG. 19 in a timing generation circuit 20 to generate a strobe signal S2 and to provide it to the strobe signal input of the predecoder 16. The output PDA0 of the predecoder 16 changes on the front edge of the strobe signal S2 as shown in FIG. 19.
However, since the time from a change in the row address signal of A8 through A15 till a change in the signal on a selected word line WL becomes long due to the delay times TD1 and TD2 at the timing generation circuits 14 and 20, the high speed operation of the memory 10 is hindered.
On the other hand, low power consumption is required in memory devices for uses in portable electronic devices.
In a synchronous DRAM, since it is provided with a plurality of banks which enables a high speed access with switching over banks in every clock pulse and operating the banks in parallel. To enable this parallel operation, latch circuits are connected, for respective word lines, at the output stage in word decoder circuits to which signals obtained by predecoding the row addresses are provided.
FIG. 20 shows a circuit for one word line, which is a part of a word decoder.
A word decoding circuit 60 is a NAND gate in which NMOS transistors 61 and 62 are connected in series, and predecoded signals SS1 and SS2 are provided to gate electrodes of the NMOS transistors 61 and 62, respectively. To select a word line WL, the predecoded signals SS1 and SS2 are made high, whereby the signal SS3 goes low. The signal SS3 is hold in a latch circuit 70, and a signal SS4 generated with inverting the signal SS3 is outputted from the latch circuit 70.
In the latch circuit 70, inverters 71 and 72 are connected in ring-shaped, and an NMOS transistor 73 for setting is connected between the output of the inverter 72 and the ground potential, and an NMOS transistor 74 for resetting is connected between the output of the inverter 71. and the ground potential.
The drive capacity of the signal SS4 is amplified by a driver 80 to drive the word line WL.
Since a memory device is activated in units of a block in order to reduce power consumption, a word reset signal WRST is commonly provided to all the latch circuits in an activated memory block when an access is finished, whereby the NMOS transistor 74 is turned on, and the signal SS4 and the word line WL goes low.
Before shipment of memories, in order to carry out an acceleration test at a high-temperature in a state where all the word lines are high, signal lines of a multiple selection signal WMSEL is commonly connected to all the latch circuits in all the word decoders. In the test, the multiple selection signals WMSEL is made high, and the NMOS transistor 73 is turned on to cause the input of the inverter 71 to go low and the output SS4 to become high.
FIG. 21 shows a structure of the latch circuit 70 in FIG. 20.
The inverter 71 is such that a PMOS transistor 711 and an NMOS transistor 712 are connected in series between the power source potentials VDD and VSS, and the both gate electrodes are commonly connected to receive the signal SS3. Similarly, the inverter 72 is such that a PMOS transistor 721 and an NMOS transistor 722 are connected in series, and the both gate electrodes are commonly connected to receive the signal SS4.
When the signal SS3 is low, the PMOS transistor 711 is on and NMOS transistor 712 is off. In this state, if the word line reset signal WRST is made high, an NMOS transistor 74 is turned on, and a through-current flows from the power source potential VDD through the PMOS transistor 711 and the NMOS transistor 74 to the power source potential VSS. When the signal SS4 goes low, the PMOS transistor 721 and NMOS transistor 722 are changed to on and off, respectively, the signal SS3 becomes high, and the PMOS transistor 711 and the NMOS transistor 712 are turned off and on, respectively, whereby the through-current is prevented. However, since the through-current flows until this state is established, useless power is consumed.
Similarly, if the multiple selection signal WMSEL is changed to high in the above high-temperature acceleration test in a state where the signal SS4 is low, the PMOS transistor 721 is on and the NMOS transistor 722 is off, a through-current is caused to flow from the power source potential VDD through the PMOS transistor 721 and the NMOS transistor 73, and the through-current continues until the signal SS4 is changed to high and the PMOS transistor 721 is turned off. In this case, since the through-current is simultaneously caused to flow in each latch circuit 70 in a chip, it cannot be disregarded. Next, the multiple selection signal WMSEL returns to low. In this state, the word line reset signal WRST is changed to high in each latch circuit 70 in all the memory blocks, whereby a through-current passing through the PMOS transistor 711 and the NMOS transistor 74 flows in each latch circuits. Therefore, the through-current cannot be disregarded. For this reason, a high-temperature acceleration test will become inaccurate.
On the other hand, since a latch circuit 70 is provided for each word line, the occupying area of the latch circuits are limited.
FIG. 22 shows a layout pattern of a diffusion area and a polysilicon wiring layer of the adjacent two latch circuits. In FIG. 22, the pattern of a metal wiring layer is not shown to avoid complication. FIG. 23 is a circuit diagram in which transistors are disposed in correspondence to the layout pattern of FIG. 22 for better understanding the pattern of FIG. 22.
In order to reduce the occupying area of the latch circuits and to narrow the width thereof, a PMOS transistor group 70P and an NMOS transistor group 70N are arrayed separately to each other and further, the PMOS transistor group 70P and the NMOS transistor group 70N are disposed along the word line direction in a band form. In FIG. 22, 721P and 711P are a p-type diffusion area of the PMOS transistors 721 and 711, respectively, while 712N, 722N, 74N and 73N are an n-type diffusion area of the NMOS transistors 712, 722, 74 and 73, respectively. The hatched areas denote polysilicon wirings, and small rectangles are between-layer contact holes. As regards the wirings of dotted patterns, the wiring at the side of the transistor group 70P is for applying a power source potential VDD to the N well, and the wiring at the side of the transistor group 70N is for applying a power source potential VSS to the P well.
If the circuit is complicated and the circuit width in the column direction is widened by providing latch circuits with through-current preventing means, the word line pitch is increased and the memory cell density is reduced, resulting in reducing the memory capacity or increasing in chip area with lengthening the width in a column direction.